Design and implementation of areaefficient interpolation filter

LI Jing, WU Xiaobo， ZHAO Jinchen
（Institute of VLSI Design, Zhejiang University, Hangzhou 310027,  China）

Abstract:  Aiming at saving the chip area , an areaefficient interpolation filter for SigmaDelta audio digitaltoanalog converter（DAC） was designed and implemented. In an effort to reduce the complexity of the system, the interpolation filter was comprised of cascade halfband filters and a sampleandhold stage. An improved structure of halfband filter was proposed to achieve the hardware efficiency. The canonic signed digital (CSD) representation was used to further reduce the area of the interpolation filter. The coefficients were attained from the Matlab simulation, and the correctness of the design was verified in FPGA. The cell area of the interpolation filter is 0.34 mm2 in TSMC 018 μm CMOS process. The experimental results indicate that the proposed interpolation filter accords with the design specification, exhibiting area efficiency.
Key words: digitaltoanalog converter(DAC); interpolation filter; halfband filter; canonic signed digital（CSD）