Research of placement of test structure in addressable test chip

SAHO Kangpeng, SHI Zheng, ZHANG Peiyong
(Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China)

Abstract: In order to relieve the disadvantage in efficiency and reliability caused by lack of automatic way in addressable test chip design, aiming to the placement of the test structure, the linear programming was investigated. After researching the manual way in placement of test structure, a set of rules was summarized and expressed as multivariate inequality, and the mathematical model based on linear programming was established and developed into an automatic placer which will help the designer finish the placement of test structure quickly and automatically. The experimental result indicates that the automatic placer can address placement of thousands of test structure in minutes, and solution is optimized in area efficiency.
Key words: addressable test chip; placement; linear programming