一种带指令高速缓存的8051 IP

作者：胡欣幸 日期：2008-11-03/span> 浏览：4221 查看PDF文档

一种带指令高速缓存的8051 IP

胡欣幸
(浙江大学 超大规模集成电路设计研究所，浙江 杭州 310027)

摘要：为设计面向AMBA的SoC集成，将8051兼容内核封装成为带32位AHB总线接口的标准主设备IP，采用了8051内核的高段外部数据空间映射成分页的4 GB SoC空间。设计中采用了嵌入式FLASH器件作为程序存储器，并为提高系统性能而设计了128字节直接映射结构的指令高速缓存。封装成的处理器IP在0.18 μm工艺下可工作在200 MHz。利用如Keil uVision等8051兼容工具进行软件开发。测试结果表明，该处理器IP在SoC集成中具有灵活性，借助软、硬件复用，提高了设计效率，具有良好的实用价值。
关键词：8051兼容内核；嵌入式FLASH程序存储器；指令高速缓存；AMBA总线；封装
中图分类号：TP368.2文献标识码：A文章编号：1001-4551(2008)10-0067-04

Wrapping 8051 core with ICACHE into a standard IP
HU Xin-xing
(The Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China)
Abstract: 8051-compatible core was wrapped with 32 bit AHB bus interface into a standard master device IP for the AMBA SoC integration. Higher part of the 8051-cores external data space was used to map the 4 GB SoC space in pages. Embedded FLASH was used as program memory, and a 128 bytes, direct-associated instruction cache was added, aiming at increasing performance. The wrapped processor can run at 200 MHz speed given 0.18 μm process is used. 8051-compatible tools like Keil uVision IDE can be used to develop software. The wrapped processor IP is flexible for SoC integration and it increases design efficiency by means of design-reuse, from which real implementations can benefit.
Key words: 8051-compatible core; embedded FLASH ROM; instruction cache(ICACHE); AMBA bus; wrap

参考文献(References):
［1］何立民.从Cygnal C8051F看8位单片机发展之路［J］.单片机与嵌入式系统应用,2002(5):5-8.
［2］KEITH C.8位微控制器如何成为系统单芯片解决方案［J］.电子与电脑,2004(7):120-123.
［3］曾晓洋,顾叶华.8位嵌入式CPU的AMBA外围接口电路:中国,200510110254.x［P］.2005-10-01.
［4］肖佐楠,于麦口.一种基于AMBA总线的8051系统微处理器应用系统:中国,200510095447.2［P］.2005-11-01.
［5］农英雄.基于FPGA的8051SOC设计［D］.沈阳：东北大学信息科学与工程学院,2006.
［6］李杰,王超,周桦.基于8051内核SoC的模拟验证与仿真［J］.单片机与嵌入式系统应用,2003(9):23-24,33.
［7］JOHN H, DAVID P. Computer Architecture: A Quantitative Approach［M］.4th ed.北京:机械工业出版社,2007.
［8］DOMINIC S. See MIPS Run, Second Edition［M］.北京:机械工业出版社,2007.