《机电工程》杂志,月刊( 详细... )
中国标准连续出版物号: ISSN 1001-4551 CN 33-1088/TH
主办单位:浙江省机电集团有限公司
浙江大学
主编:陈 晓
副 主 编:唐任仲、罗向阳(执行主编)
总 经 理:罗向阳
出 版:浙江《机电工程》杂志社有限公司
地 址:杭州市上城区延安路95号浙江省机电集团大楼二楼211、212室
电话Tel:+86-571-87041360、87239525
E-mail:meem_contribute@163.com
国外发行:中国国际图书贸易总公司
订阅:全国各地邮局 国外代号:M3135
国内发行:浙江省报刊发行局
邮发代号:32-68
广告发布登记证:杭上市管广发G-001号
在线杂志 |
当前位置: 机电工程 >>在线杂志 |
双重图形技术的优化设计
作者:潘意杰,陈晔 日期:2008-12-26/span> 浏览:3525 查看PDF文档
双重图形技术的优化设计
潘意杰,陈晔
(浙江大学 超大规模集成电路研究所, 浙江 杭州 310027)
摘要:作为集成电路光刻设计下一节点发展的候选之一,双重图形技术(DPT)面临的诸多复杂过程将影响其在制造领域的迅速应用,其中最突出的因素是设计的复杂度和数据量急剧增长。通过分析版图分解问题和光学邻近校正(OPC)中的信息重用,在重分解修正后的版图与前次OPC数据-分段和段偏移量之间建立了关联,并进行了相关实验。实验结果表明,在保证版图校正精确度的同时,可节省大量的运行时间,同时也有效地缩短了DPT的流程。
关键词:可制造性设计;双重图形技术;光学邻近校正;分辨率增强技术;重用
中图分类号:TN305.7文献标识码:A文章编号:1001-4551(2008)12-0035-04
Optimization design for double patterning technology
PAN Yi-jie, CHEN Ye
(Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China)
Abstract: As one of candidates for next node in lithography of integrated circuit(IC), double patterning technology(DPT) has complicated process steps that may prevent it from being utilized in production. The most concerned factor is that its complexity and data volume increase dramatically. By analyzing decomposition problems and optical proximity correction(OPC) reuse scheme based on segments, a relationship was set up between changed layout from re-split and previous OPC data, namely fragmentation and offset information. Experiments are carried out and show that a large amount of runtime is saved while keeping the same satisfied results and the circle in DPT is shortened efficiently.
Key words: design for manufacturability(DFM); double patterning technology(DPT); optical proximity correction(OPC); resolution enhancement technology(RET); reuse
参考文献(References):
[1]BALASINSKI A. Patterning Techniques for Next Generation ICs[C]//Proceedings of SPIE, Microelectronics: Design, Technology, and Packaging Ⅲ. SanDiego:[s.n.],2007:1-5.
[2]KIM S M, KOO S Y, CHOI J S, et al. Issues and Challenges of Double Patterning Lithography in DRAM[C]//Proceedings of SPIE, Optical Microlithography XX. SanDiego:[s.n.],2007:1-7.
[3]LUCAS K, CORK C, MILOSLAVSKY A, et al. Interactions of Double Patterning Technology with Wafer Processing, OPC and design flows[C]//Proceedings of SPIE, Optical Microlithography XXI. SanDiego:[s.n.],2008:1-12.
[4]DRAPEAU M. Double Patterning Design Split Implementation and Validation for the 32nm Node[C]//Proceedings of SPIE, Design for Manufacturability through Design-Process Integration. SanDiego: [s.n.],2007:1-15.
[5]LIM C M. Positive and Negative Tone Double Patterning Lithography for 50nm Flash Memory[C]//Proceedings of SPIE,Optical Microlithography XIX. Orlando:[s.n.],2006:1-8.
[6]TOYAMA N. Approach to Analyze Decomposition Impact for Photomask Fabrication[C]//Proceedings of SPIE, Photomask and Next-Generation Lithography Mask Technology XIV. SanDiego:[s.n.],2007:1-9.
[7]BAILEY G. Double Pattern EDA Solution for 32nm HP and Beyond[C]//Proceedings of SPIE, Design for Manufacturability through Design-Process Integration. SanDiego:[s.n.],2007:1-12.
[8]ZHANG H B, SHI Z. SOFT: Smooth OPC Fixing Technique for ECO Process[C]//Proceedings of SPIE, Design for Manufacturability through Design-Process Integration. USA: [s.n.],2007:1-9.
[9]WANG X, PILLOFF M, TANG H, et al. Exploiting Hierarchical Structure to Enhance Cell-based RET with Localized OPC Reconfiguration[C]// Proceedings of SPIE, Design and Process Integrated for Microelectronic Manufacturing Ⅲ. SanDiego:[s.n.],2005:361-367.
友情链接