基于CKCore的处理器SDIO接口主控制器设计*

作者：车向勇，薛 念，潘 赟*，严晓浪 日期：2010-11-22/span> 浏览：3160 查看PDF文档

基于CKCore的处理器SDIO接口主控制器设计*
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车向勇，薛 念，潘 赟*，严晓浪

（浙江大学 超大规模集成电路设计研究所，浙江 杭州 310027）
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摘要：作为具有自主知识产权的国产嵌入式CPU核，CKCore系列处理器核已广泛应用于嵌入式各领域。为满足基于CKCore内核的处理器芯片的各类应用需求，需开发功能强大的芯片外围扩展接口。介绍了一种具有广阔应用前景的片外扩展接口，即SDIO接口。在分析了SDIO接口工作原理的基础上，开发了基于CKCore的处理器SDIO接口主控制器IP核。利用RVM方法进行硬件RTL代码功能验证，通过CKSOC开发平台完成了FPGA原型验证，同时给出了DC综合结果。实验结果表明，该自行开发的IP核工作正常，性能良好，有效提高了CKCore处理器的外围扩展能力。
关键词：〗CKCore；SDIO接口；设计；验证
中图分类号：TP3；TN402
文献标识码：A文章编号：1001-4551(2010)10-0085-05

Design of SDIO host controller of CKCore based processor
CHE Xiangyong, XUE Nian, PAN Yun, YAN Xiaolang
(Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China)
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Abstract: As a domestic embedded CPU core of proprietary intellectual property rights, CKCore has been widely used in various situations. In order to meet various application needs of CKCore based processors, more powerful peripheral interfaces are required. A kind of peripheral extension interface was introduced, which has a bright future for applicationSDIO interface. Based on the analysis of the SDIO specification, a SDIO Host Controller IP of CKCore based processor was developed. The IP verification was done under RVM platform and also FPGA platform. The design was synthesized in Synopsys DC. The results indicate that this selfdeveloped IP has been reasonably designed and works well, which improves the peripheral extension capability of the CKCore based processor.
Key words: CKCore; SDIO interface; design; verification