Design of FIFO based on DDR2 SDRAM

ZHAN Hongwu, XV Fang
(College of Mechanical Engineering, Zhejiang University of Teehnology, Hangzhou 310014，China)

Abstract：Aiming at the growing demand of FIFO depth and the lower storage density of SRAM technology in many applications, a FIFO access control solution for DDR2 in FPGA was proposed. The scheme was composed by a DDR2 controller with lower access latency， to achieve selfrefresh， memory access scheduling， address decoding and other operations， and an access interface compatible with typical synchronous FIFO memories.  Some special feature on DDR2 specification was focused on， and a DDR2 controller state machine with lowaccess latency was given. The FIFO interface was designed to support parallel data reading and writing in a fixed access cycle. The testing results indicate that the FIFO interface has a high access rate， and the depth of the FIFO system can be configured.
Key words：first input first output (FIFO)；DDR2；state machine；fieldprogrammable gate array(FPGA)