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Board-level electronic packaging drop failure analysis
Published:2013-08-13 author:JIN Chao-chao, XV Yang-jian, LIANG Li-hua Browse: 3239 Check PDF documents

Board-level electronic packaging drop failure analysis

JIN Chao-chao, XV Yang-jian, LIANG Li-hua
(College of Mechanical Engineering, Zhejiang University of Technology, Hangzhou 310032, China)

Abstract:Aiming at the drop reliability of TFBGA package,a 3D finite model based on JEDEC standard was built. Input-G method was adopted and strain-rate effect of the solder joint was considered to investigate the dynamic response and the failure process of electronic packaging structure,at the same time,the failure distribution of the structure was obtained by simulating with a cohesive zone model. Finally,influence of solder height and diameter on its impact reliability was studied. The simulation results show that repeated bending of PCB induced by the shock wave is the fundamental reason to cause the interface failure of solder balls. The larger stress appears at the outmost solder joints,which are easily damaged key solder joints accordingly. The failures are mainly located at IMC near to the PCB side of the key solder joints and caused by the inconsistent warpage of PCB and packaging components. Present parametric modeling and comparison between different sizes of models can provide a significant reference for the optimal design of electronic packaging structure.
Key words:printed circuit board(PCB);board-level drop;reliability;electronic packaging;strain-rate effect;cohesive zone model; failure analysis
 

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